Research Information System
IEEE Transactions on Circuits and Systems II: Express Briefs, vol.73, no.2, pp.208-212, 2026 (SCI-Expanded, Scopus)
This brief presents a 1024-point radix-2 memory-based fast Fourier transform (FFT) architecture. This work aims to achieve a normal order at both the input and the output without requiring an additional circuit or memory. The proposed architecture is the first memory-based FFT to utilize a serial commutator (SC) kernel as a processing element (PE). This halves the number of adders and multipliers. Likewise, a novel address generation circuit is presented. It produces the same memory read and write addresses for both memories, as well as conflict-free access. The proposed architecture has been implemented on a Virtex 7 field-programmable gate array (FPGA). The experimental results indicate that it achieves low area, efficient resource utilization, and low power consumption.