Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage

Creative Commons License

KAYA Z., Garrido M., Takala J.

IEEE Transactions on Circuits and Systems II: Express Briefs, cilt.70, sa.8, ss.3084-3088, 2023 (SCI-Expanded) identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 70 Sayı: 8
  • Basım Tarihi: 2023
  • Doi Numarası: 10.1109/tcsii.2023.3245823
  • Dergi Adı: IEEE Transactions on Circuits and Systems II: Express Briefs
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Aerospace Database, Applied Science & Technology Source, Communication Abstracts, Compendex, Computer & Applied Sciences, INSPEC, Metadex, Civil Engineering Abstracts
  • Sayfa Sayıları: ss.3084-3088
  • Anahtar Kelimeler: Memory-based FFT, perfect shuffle, radix-2
  • Bilecik Şeyh Edebali Üniversitesi Adresli: Evet

Özet

This brief presents a new P -parallel radix-2 memory-based fast Fourier transform (FFT) architecture. The aim of this brief is to reduce the number of multiplexers and achieve an efficient memory usage. One advantage of the proposed architecture is that it only needs permutation circuits after the memories, which reduces the multiplexer usage to only one multiplexer per parallel branch. Another advantage is that the architecture calculates the same permutation based on the perfect shuffle at each iteration. Thus, the shuffling circuits do not need to be configured for different iterations. In fact, all the memories require the same read and write addresses, which simplifies the control even further and allows to merge the memories. Along with the hardware efficiency, conflict-free memory access is fulfilled by a circular counter. The FFT has been implemented on a field programmable gate array. Compared to previous approaches, the proposed architecture has the least number of multiplexers and achieves very low area usage.